NT5DS128M4CG Datasheet, Nanya Techology

* DDR 512M bit, Die C, based on 90nm design rules
* Double data rate architecture: two data transfers per clock cycle
* Bidirectional data strobe (DQS) is tra.

Die C of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 90 nm design process. The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank.