Unit Loading Fan Out
Pin Names
Description
A0 – A3
B0 – B3
C0
S0 – S3
C4
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
54F 74F
UL
HIGH LOW
10 20
10 20
10 10
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b1 2 mA
20 mA b1 2 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C0) The binary sum appears on the Sum
(S0 – S3) and outgoing carry (C4) outputs The binary weight
of the various inputs and outputs is indicated by the sub-
script numbers representing powers of two
20 (A0 a B0 a C0) a 21 (A1 a B1)
a 22 (A2 a B2) a 23 (A3 a B3)
e S0 a 2S1 a 4S2 a 8S3 a 16C4
Where (a) e plus
Interchanging inputs of equal weight does not affect the op-
eration Thus C0 A0 B0 can be arbitrarily assigned to pins
5 6 and 7 for DIPS and 7 8 and 9 for chip carrier packages
Due to the symmetry of the binary add function the ’F283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic) See Figure 1 Note that if C0 is not used it
must be tied LOW for active HIGH logic or tied HIGH for
active LOW logic
Due to pin limitations the intermediate carries of the ’F283
are not brought out for use as inputs or outputs However
other means can be used to effectively insert a carry into or
bring a carry out from an intermediate stage Figure 2
shows how to make a 3-bit adder Tying the operand inputs
of the fourth adder (A3 B3) LOW makes S3 dependent only
on and equal to the carry from the third adder Using some-
what the same principle Figure 3 shows a way of dividing
the ’F283 into a 2-bit and a 1-bit adder The third stage
adder (A2 B2 S2) is used merely as a means of getting a
carry (C10) signal into the fourth stage (via A2 and B2) and
bringing out the carry from the second stage on S2 Note
that as long as A2 and B2 are the same whether HIGH or
LOW they do not influence S2 Similarly when A2 and B2
are the same the carry into the third stage does not influ-
ence the carry out of the third stage Figure 4 shows a meth-
od of implementing a 5-input encoder where the inputs are
equally weighted The outputs S0 S1 and S2 present a bina-
ry number equal to the number of inputs I1 – I5 that are true
Figure 5 shows one method of implementing a 5-input ma-
jority gate When three or more of the inputs I1 – I5 are true
the output M5 is true
C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4
Logic Levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1
Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0
Active HIGH 0 a 10 a 9 e 3 a 16 Active LOW 1 a 5 a 6 e 12 a 0
FIGURE 1 Active HIGH versus Active LOW Interpretation
2
