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National Semiconductor Electronic Components Datasheet

74F379 Datasheet

Quad Parallel Register with Enable

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August 1995
54F 74F379
Quad Parallel Register with Enable
General Description
The ’F379 is a 4-bit register with buffered common Enable
This device is similar to the ’F175 but features the common
Enable rather than common Master Reset
Features
Y Edge triggered D-type inputs
Y Buffered positive edge-triggered clock
Y Buffered common enable input
Y True and complement outputs
Y Guaranteed 4000V minimum ESD protection
Commercial
74F379PC
74F379SC (Note 1)
74F379SJ (Note 1)
Military
54F379DM (QB)
54F379FM (QB)
54F379LM (QB)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 300 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9527–5
TL F 9527 – 1
TL F 9527 – 2
TL F 9527–3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9527
RRD-B30M115 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F379 Datasheet

Quad Parallel Register with Enable

No Preview Available !

Unit Loading Fan Out
54F 74F
Pin Names
Description
U L Input IIH IIL
HIGH LOW Output IOH IOL
E
D0 – D3
CP
Q0 – Q3
Q0 – Q3
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
Complement Outputs
10 10
10 10
10 10
50 33 3
50 33 3
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F379 consists of four edge-triggered D-Type flip-flops
with individual D inputs and Q and Q outputs The Clock
(CP) and Enable (E) inputs are common to all flip-flops
When the E is input HIGH the register will retain the present
data independent of the CP input The Dn and E inputs can
change when the clock is in either state provided that the
recommended setup and hold times are observed
Truth Table
Inputs
E CP Dn
HL
LL
LL
X
H
L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Transition
NC e No Change
Logic Diagram
Outputs
Qn Qn
NC NC
HL
LH
TL F 9527 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F379
Description Quad Parallel Register with Enable
Maker National
Total Page 8 Pages
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