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74F533 Datasheet

Octal Transparent Latch with TRI-STATE Outputs

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May 1995
54F 74F533
Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’F533 consists of eight latches with TRI-STATE outputs
for bus organized system applications The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH
When LE is LOW the data that meets the setup times is
latched Data appears on the bus when the Output Enable
(OE) is LOW When OE is HIGH the bus output is in the high
impedance state The ’F533 is the same as the ’F373 ex-
cept that the outputs are inverted
Features
Y Eight latches in a single package
Y TRI-STATE outputs for bus interfacing
Y Inverted version of the ’F373
Y Guaranteed 4000V minimum ESD protection
Commercial
74F533PC
74F533SC (Note 1)
74F533SJ (Note 1)
Military
54F533DM (Note 2)
54F533FM (Note 2)
54F533LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9548–4
TL F 9548 – 2
TL F 9548 – 3
TL F 9548–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9548
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F533 Datasheet

Octal Transparent Latch with TRI-STATE Outputs

No Preview Available !

Unit Loading Fan Out
Pin Names
D0 – D7
LE
OE
O0 – O7
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Function Table
Inputs
LE OE
HL
HL
LL
XH
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
D
H
L
X
X
Output
O
L
H
O0
Z
Functional Description
The ’F533 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
Logic Diagram
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
TL F 9548 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F533
Description Octal Transparent Latch with TRI-STATE Outputs
Maker National
Total Page 8 Pages
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