Datasheet4U Logo Datasheet4U.com

100310 - Low Skew 2:8 Differential Clock Driver

Description

The 100310 is a low skew a bit differential clock driver which is designed to select between two separate differen

tial clock inputs.

The low output to output skew « 50 ps) is maintained for either clock input.

A LOW on the select pin (SEL) selects CLKINA.

Features

  • Low output to output skew.
  • Differential inputs and outputs.
  • Allows multiplexing between two clock inputs.
  • Voltage compensated operating range: -4.2V to -5.7V Ordering Code: See Section 5 Logic Symbol CLKINA ClKINA CLKINB CLKINB SEL ClKg CLKg CLKj CLKj CLK2 CLK2 ClK3 CLK3 CLK. CLK. CLKs CLKs CLKs CLKs ClK7 CLK7 --t>--vss Tl/F/10943-1 Connection Diagram 28-Pln pcc rn ClKe ClKe ax7VCCAax7 NC ClKINB [TI [Q] [!] [l][IIIII Pin Names CLKINn.
  • ClKINn SEL.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
1003GD LED Lamp Everlight Electronics
100-267 Thin Film Vishay
100-GC6NLT1 GAS EnGinE-GEnErAtor SEt MTU Onsite Energy
100-JC6DT3 DIESEL ENGINE-GENERATOR SET MTU Onsite Energy
100-JS6DT3 DIESEL ENGINE-GENERATOR SET MTU Onsite Energy

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
100311 Low Skew 1:9 Differential Clock Driver
100315 Low-Skew Quad Clock Driver
100136DC 4-STAGE COUNTER/ SHIFT REGISTER

Full PDF Text Transcription

Click to expand full text
.o... CW) .oo... ~National D Semiconductor 100310 Low Skew 2:8 Differential Clock Driver General Description The 100310 is a low skew a·bit differential clock driver which is designed to select between two separate differen· tial clock inputs. The low output to output skew « 50 ps) is maintained for either clock input. A LOW on the select pin (SEL) selects CLKINA. CLKINA and a HIGH on the SEl pin selects the CLKINS. ClKINS inputs. The 100310 is ideal for those applications that need the ability to freely select between two clocks. or to maintain the ability to switch to an alternate or backup clock should a problem arise with the primary clock source. A Vss output is provided for single-ended operation.
Published: |