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National Semiconductor Electronic Components Datasheet

5474 Datasheet

Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs

No Preview Available !

June 1989
5474 DM5474 DM7474
Dual Positive-Edge-Triggered D Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs The informa-
tion on the D input is accepted by the flip-flops on the posi-
tive going edge of the clock pulse The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not
violated A low logic level on the preset or clear inputs will
set or reset the outputs regardless of the logic levels of the
other inputs
Features
Y Alternate Military Aerospace device (5474) is available
Contact a National Semiconductor Sales Office Distrib-
utor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6526 – 1
Order Number 5474DMQB 5474FMQB DM5474J DM5474W DM7474M or DM7474N
See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs
Outputs
PR CLR CLK D
Q
Q
LH
X XH L
HL
X XL H
LL
X
XH
H
H H u HH L
H H u LL H
HH
L X Q0 Q0
H e High Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
u e Positive-going transition of the clock
e This configuration is nonstable that is it will not persist when either the preset and or clear
inputs return to their inactive (high) level
Q0 e The output logic level of Q before the indicated input conditions were established
C1995 National Semiconductor Corporation TL F 6526
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

5474 Datasheet

Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs

No Preview Available !

Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54 and 54
b55 C to a125 C
DM74
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM5474
Min Nom
VCC
VIH
VIL
IOH
IOL
fCLK
tW
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 2)
Pulse Width
(Note 2)
Clock High
Clock Low
45 5
2
0
30
37
Clear Low
30
Preset Low
30
utSU
Input Setup Time (Notes 1 2)
20
utH
Input Hold Time (Notes 1 2)
5
TA
Free Air Operating Temperature
b55
uNote 1 The symbol ( ) indicates the rising edge of the clock pulse is used for reference
Note 2 TA e 25 C and VCC e 5V
Max
55
08
b0 4
16
15
125
Min
4 75
2
0
30
37
30
30
20u
5u
0
DM7474
Nom
5
Max
5 25
08
b0 4
16
15
70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 3)
Max
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current Max
Input Voltage
VCC e Min II e b12 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
b1 5
34
02 04
1
IIH
High Level Input
VCC e Max
D
Current
VI e 2 4V
Clock
40
80
Clear
120
Preset
40
IIL
Low Level Input
VCC e Max
D
Current
VI e 0 4V
Clock
(Note 6)
Clear
b1 6
b3 2
b3 2
Preset
b1 6
IOS Short Circuit
Output Current
VCC e Max
(Note 4)
DM54
DM74
b20
b18
b55
b55
ICC Supply Current
VCC e Max (Note 5)
Note 3 All typicals are at VCC e 5V TA e 25 C
Note 4 Not more than one output should be shorted at a time
17 30
Note 5 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
Note 6 Clear is tested with preset high and preset is tested with clear high
Units
V
V
V
mA
mA
mA
mA
mA
2


Part Number 5474
Description Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs
Maker National Semiconductor
Total Page 6 Pages
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