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54AC169 Datasheet

4-Stage Synchronous Bidirectional Counter

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July 1998
54AC169 54ACT169
4-Stage Synchronous Bidirectional Counter
General Description
The ’AC/’ACT169 is fully synchronous 4-stage up/down
counter. The ’AC/’ACT169 is a modulo-16 binary counter. It
features a preset capability for programmable operation,
carry lookahead for easy cascading and a U/D input to con-
trol the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the
LOW-to-HIGH transition of the Clock.
n Synchronous counting and loading
n Built-In lookahead carry capability
n Presettable for programmable operation
n Outputs source/sink 24 mA
n ’ACT has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
5962-91603
Features
n ICC reduced by 50%
Logic Symbols
DS100276-1
IEEE/IEC
Pin
Names
CEP
CET
CP
P0– P3
PE
U/D
Q0– Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Data Inputs
Parallel Enable Input
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output
DS100276-2
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100276
www.national.com


National Semiconductor Electronic Components Datasheet

54AC169 Datasheet

4-Stage Synchronous Bidirectional Counter

No Preview Available !

Connection Diagrams
Pin Assignment
for DIP and Flatpak
Logic Diagram
DS100276-3
Pin Assignment
for LCC
DS100276-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
DS100276-5
Functional Description
The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops
and have no constraints on changing the control or data in-
put signals in either state of the Clock. The only requirement
is that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The parallel
load operation takes precedence over the other operations,
as indicated in the Mode Select Table. When PE is LOW, the
data on the P0–P3 inputs enters the flip-flops on the next ris-
ing edge of the Clock. In order for counting to occur, both
CEP and CET must be LOW and PE must be HIGH; the U/D
input then determines the direction of counting. The Terminal
Count (TC) output is normally HIGH and goes LOW, pro-
vided that CET is LOW, when a counter reaches zero in the
Count Down mode or reaches 15 in the Count Up mode. The
TC output state is not a function of the Count Enable Parallel
(CEP) input level. If an illegal state occurs, the ’AC169 will
return to the legitimate sequence within two counts. Since
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2


Part Number 54AC169
Description 4-Stage Synchronous Bidirectional Counter
Maker National Semiconductor
Total Page 10 Pages
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