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National Semiconductor Electronic Components Datasheet

54ACQ373 Datasheet

Quiet Series Octal Transparent Latch

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September 1998
54ACQ373 54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE®
Outputs
General Description
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT373
n 4 kV minimum ESD immunity (’ACQ)
n Standard Military Drawing (SMD)
— ’ACTQ373: 5962-92188
— ’ACQ373: 5962-92178
Logic Symbols
IEEE/IEC
DS100238-1
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
DS100238-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100238
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National Semiconductor Electronic Components Datasheet

54ACQ373 Datasheet

Quiet Series Octal Transparent Latch

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP and Flatpak
Pin Assignment
for LCC
DS100238-3
Functional Description
The ’ACQ/’ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Logic Diagram
DS100238-4
Truth Table
Inputs
Outputs
LE OE Dn
XHX
On
Z
HL L
L
HLH
H
LLX
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH to Low transition of Latch Enable
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2


Part Number 54ACQ373
Description Quiet Series Octal Transparent Latch
Maker National Semiconductor
Total Page 8 Pages
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