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National Semiconductor Electronic Components Datasheet

54ACT257 Datasheet

Quad 2-Input Multiplexer

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July 1998
54AC257 54ACT257
Quad 2-Input Multiplexer with TRI-STATE® Outputs
General Description
The ’AC/’ACT257 is a quad 2-input multiplexer with
TRI-STATE outputs. Four bits of data from two sources can
be selected using a Common Data Select input. The four
outputs present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE) in-
put, allowing the outputs to interface directly with
bus-oriented systems.
Features
n ICC and IOZ reduced by 50%
n Multiplexer expansion by tying outputs together
n Noninverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT257 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC257: 5962-88703
— ’ACT257: 5962-89689
Logic Symbols
IEEE/IEC
DS100286-1
Pin Names
S
OE
I0a– I0d
I1a– I1d
Za– Zd
Description
Common Data Select Input
TRI-STATE Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
TRI-STATE Multiplexer Outputs
DS100286-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100286
www.national.com


National Semiconductor Electronic Components Datasheet

54ACT257 Datasheet

Quad 2-Input Multiplexer

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP and Flatpak
DS100286-3
Pin Assignment for LCC
DS100286-4
Logic Diagram
Functional Description
The ’AC/’ACT257 is quad 2-input multiplexer with
TRI-STATE outputs. It selects four bits of data from two
sources under control of a Common Data Select input. When
the Select input is LOW, the I0x inputs are selected and when
Select is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted)
form. The device is the logic implementation of a 4-pole,
2-position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Za = OE (11a S + I0a S)
Zb = OE (11b S + I0b S)
Zc = OE (11c S + I0c S)
Zd = OE (11d S + I0d S)
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied to-
gether, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to TRI-STATE devices whose outputs are tied together are
designed so there is no overlap.
Truth Table
Output
Select
Enable
Input
OE S
HX
LH
LH
LL
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Data
Inputs
I0 I1
XX
XL
XH
LX
HX
Outputs
Z
Z
L
H
L
H
DS100286-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2


Part Number 54ACT257
Description Quad 2-Input Multiplexer
Maker National Semiconductor
Total Page 8 Pages
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