54F273 Datasheet - National Semiconductor

Octal D Flip-Flop

54F273 Features

* Y Ideal buffer for MOS microprocessor or memory Y Eight edge-triggered D flip-flops Y Buffered common clock Y Buffered asynchronous Master Reset Y See ’F377 for clock enable version Y See ’F373 for transparent latch version Y See ’F374 for TRI-STATE version Y Guaranteed 4000V minimum ESD protection

54F273 General Description

The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to.

54F273 Datasheet (363.35 KB)

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54F273

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National Semiconductor

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363.35 KB

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Octal d flip-flop.

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54F273 Octal Flip-Flop National Semiconductor

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54F273 Features

54F273 General Description

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