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54F273 Key Features

  • 5 RRD-B30M75 Printed in U S A
  • D7 MR CP Q0
  • 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to est

54F273 Description

The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW...