* Y VCC (Max) b VOL RMIN e IOL b N3 (IIL) Where N1 (IOH) e total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) e total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) e total maximum input low current for all inputs tied to pull-up resistor
54LS03
National Semiconductor
127.11 KB
Quad 2-input nand gates.
54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs June 1989 54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Co.
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