quad 2-input nand gates.
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VCC (Max) b VOL RMIN e IOL b N3 (IIL) Where N1 (IOH) e total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) e total maximum input high c.
This device contains four independent gates each of which performs the logic NAND function The open-collector outputs require external pull-up resistors for proper logical operation
Pull-Up Resistor Equations
RMAX e VCC (Min) b VOH N1 (IOH) a N2 (II.
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