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54LS175 - Hex/Quad D Flip-Flops

Download the 54LS175 datasheet PDF (54LS174 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for hex/quad d flip-flops.

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outpu

Features

  • Y LS174 contains six flip-flops with single-rail outputs Y LS175 contains four flip-flops with double-rail outputs Y Buffered clock and direct clear inputs Y Individual data input to each flip-flop Y.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (54LS174-NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by National Semiconductor
  • 54LS173 - 4-Bit D-Type Register
  • 54LS174 - Hex/Quad D Flip-Flops
  • 54LS10 - Triple 3-Input NAND Gates
  • 54LS109 - Dual Positive-Edge-Triggered J-K Flip-Flops
  • 54LS11 - Triple 3-Input AND Gates
  • 54LS114 - Dual JK Flip-Flop
  • 54LS13 - DUAL 4-INPUT SCHMITT TRIGGER
  • 54LS133 - 13-INPUT NAND GATE

Full PDF Text Transcription

Click to expand full text
54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear June 1989 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output Fea
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