54LS256 Datasheet - National Semiconductor

Dual 4-Bit Addressable Latch

54LS256 Features

* Y Serial-to-parallel capability Y Output from each storage bit available Y Random (addressable) data entry Y Easily expandable Y Active low common clear Connection Diagram Logic Symbol Dual-In-Line Package TL F 9823

* 1 Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Numbe

54LS256 General Description

The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 * Q3) When the Enable (E) is HIGH and the Clear input (CL) i.

54LS256 Datasheet (118.21 KB)

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54LS256

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National Semiconductor

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118.21 KB

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Dual 4-bit addressable latch.

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54LS256 Dual 4-Bit Addressable Latch National Semiconductor

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54LS256 Features

54LS256 General Description

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