Datasheet Details
| Part number | 54LS42 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 120.14 KB |
| Description | BCD/Decimal Decoders |
| Datasheet |
 54LS42 Datasheet
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| Part number | 54LS42 |
|---|---|
| Manufacturer | National Semiconductor (now Texas Instruments) |
| File Size | 120.14 KB |
| Description | BCD/Decimal Decoders |
| Datasheet |
54LS42 Datasheet
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These BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions Connection Diagram Dual-In-Line Package TL F 6365 – 1 Order Number 54LS42DMQB 54LS42FMQB DM54LS42J DM54LS42W DM74LS42M or DM74LS42N See NS Package Number J16A M16A N16E or W16A Logic Diagram
54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders June 1989 54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders.
| Part Number | Description |
|---|---|
| 54LS49 | BCD to 7-Segment Decoder |
| 54LS00 | Quad 2-Input NAND Gates |
| 54LS02 | Quad 2-Input NOR Gates |
| 54LS03 | Quad 2-Input NAND Gates |
| 54LS04 | Hex Inverting Gates |
| 54LS05 | HEX INVERTERS |
| 54LS08 | Quad 2-Input AND Gates |
| 54LS09 | QUAD 2-INPUT AND GATES |
| 54LS10 | Triple 3-Input NAND Gates |
| 54LS109 | Dual Positive-Edge-Triggered J-K Flip-Flops |