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National Semiconductor Electronic Components Datasheet

74AC378 Datasheet

Parallel D Register

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March 1993
54AC 74AC378
Parallel D Register with Enable
General Description
The ’AC378 is a 6-bit register with a buffered common En-
able This device is similar to the ’AC174 but with common
Enable rather than common Master Reset
Features
Y 6-bit high-speed parallel register
Y Positive edge-triggered D-type inputs
Y Fully buffered common clock and enable inputs
Y Input clamp diodes limit high-speed termination effects
Y Standard Military Drawing (SMD)
’AC378 5962-91605
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 10231–1
IEEE IEC
TL F 10231 – 2
TL F 10231 – 3
TL F 10231–4
Pin Names
E
D0 – D5
CP
Q0 – Q5
Description
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Outputs
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10231
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74AC378 Datasheet

Parallel D Register

No Preview Available !

Functional Description
The ’AC378 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q inputs The Clock (CP) and
Enable (E) inputs are common to all flip-flops
When the E input is LOW new data is entered into the
register on the LOW-to-HIGH transition of the CP input
When the E input is HIGH the register will retain the present
data independent of the CP input
Logic Diagram
Truth Table
Inputs
E CP Dn
HLX
L LH
LLL
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Output
Qn
No Change
H
L
TL F 10231 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74AC378
Description Parallel D Register
Maker National Semiconductor
Total Page 8 Pages
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