Pin Names
A0 – A7
B0 – B7
APAR BPAR
ODD EVEN
GBA GAB
SEL
LEA LEB
ERRA ERRB
www.DataSheet4U.com
Description
A Bus Data Inputs Data Outputs
B Bus Data Inputs Data Outputs
A and B Bus Parity Inputs
ODD EVEN Parity Select Active
LOW for EVEN Parity
Output Enables for A or B Bus
Active LOW
Select Pin for Feed-Through or
Generate Mode LOW for Generate
Mode
Latch Enables for A and B Latches
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In
LOW if Error Occurs
Functional Description
The ’AC ’ACT899 has three principal modes of operation
which are outlined below These modes apply to both the A-
to-B and B-to-A directions
Bus A (B) communicates to Bus B (A) parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR) If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW
the parity generated from B 0 7 (A 0 7 ) can be
checked and monitored by ERRB (ERRA)
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data parity bit
error to the CPU)
Independent Latch Enables (LEA and LEB) allow other
permutations of generating checking (see Function Ta-
ble below)
Function Table
Inputs
GAB GBA SEL LEA LEB
Operation
H H X X X Busses A and B are TRI-STATE
H L L L H Generates parity from B 0 7 based on O E (Note 1) Generated parity
x APAR Generated parity checked against BPAR and output as
ERRB
xH L L H H Generates parity from B 0 7 based on O E Generated parity
APAR Generated parity checked against BPAR and output as ERRB
Generated parity also fed back through the A latch for generate check
as ERRA
H L L X L Generates parity from B latch data based on O E Generated parity
x APAR Generated parity checked against latched BPAR and
output as ERRB
xH L H X H BPAR B 0 7
APAR A0 7 Feed-through mode Generated parity
checked against BPAR and output as ERRB
xH L H H H BPAR B 0 7
APAR A 0 7
Feed-through mode Generated parity checked against BPAR and
output as ERRB Generated parity also fed back through the A latch for
generate check as ERRA
xL H L H L Generates parity for A 0 7 based on O E Generated parity
BPAR Generated parity checked against APAR and output as ERRA
xL H L H H Generates parity from A 0 7 based on O E Generated parity
BPAR Generated parity checked against APAR and output as ERRA
Generated parity also fed back through the B latch for generate check
as ERRB
L H L L X Generates parity from A latch data based on O E Generated parity
x BPAR Generated parity checked against latched APAR and
output as ERRA
xL H H H L APAR A 0 7
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA
xL H H H H APAR A 0 7
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA Generated parity also fed back through the B latch for
generate check as ERRB
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Note 1 O E e ODD EVEN
2
