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National Semiconductor Electronic Components Datasheet

74ACTQ16374 Datasheet

16-Bit D Flip-Flop

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March 1993
54ACTQ 74ACTQ16374
16-Bit D Flip-Flop with TRI-STATE Outputs
General Description
The ’ACTQ16374 contains sixteen non-inverting D flip-flops
with TRI-STATE outputs and is intended for bus oriented
applications The device is byte controlled A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation
The ’ACTQ16245 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance FACT Quiet SeriesTM features
GTOTM output control for superior performance
Features
Y Utilizes NSC FACT Quiet Series technology
Y Guaranteed simultaneous switching noise level and
dynamic threshold performance
Y Guaranteed pin-to-pin output skew
Y Buffered Positive edge-triggered clock
Y Separate control logic for each byte
Y 16-bit version of the ’ACTQ374
Y Outputs source sink 24 mA
Y Additional specs for Multiple Output Switching
Y Output loadings specs for both 50 pF and 250 pF loads
Logic Symbol
Connection Diagram
Pin Assignment for
SSOP and CERPAK
TL F 10935 – 1
Pin Description
Pin
Names
OEn
CPn
I0 – I15
O0 – O15
Description
Output Enable Input (Active Low)
Clock Pulse Input
Inputs
Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10935
TL F 10935 – 2
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74ACTQ16374 Datasheet

16-Bit D Flip-Flop

No Preview Available !

Functional Description
The ’ACTQ16374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and TRI-STATE true out-
puts The device is byte controlled with each byte function-
ing identically but independent of the other The control
pins can be shorted together to obtain full 16-bit operation
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte The description
which follows applies to each byte Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition With the Output Enable (OEn) LOW the contents
of the flip-flops are available at the outputs When OEn is
HIGH the outputs go to the high impedance state Opera-
tion of the OEn input does not affect the state of the flip-
flops
Truth Tables
Inputs
CP1 OE1
LL
LL
LL
XH
Inputs
CP2 OE2
LL
LL
LL
XH
H e High Voltage Level
L e Low Voltage Level
X e Immaterial
Z e High Impedance
Logic Diagrams
Byte 1 (0 7)
I0 – I7
H
L
X
X
I8 – I15
H
L
X
X
Outputs
O0 – O7
H
L
(Previous)
Z
Outputs
O8 – O15
H
L
(Previous)
Z
Byte 2 (8 15)
TL F 10935 – 3
TL F 10935 – 4
2


Part Number 74ACTQ16374
Description 16-Bit D Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
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