Unit Loading Fan Out
Pin Names
CE
CP
P0 – P3
PL
UD
Q0 – Q3
RC
TC
Description
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output (Active LOW)
Terminal Count Output (Active HIGH)
54F 74F
UL
HIGH LOW
10 30
10 10
10 10
10 10
10 10
50 33 3
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b1 8 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F190 is a synchronous up down BCD decade counter
containing four edge-triggered flip-flops with internal gating
and steering logic to provide individual preset count-up and
count-down operations It has an asynchronous parallel
load capability permitting the counter to be preset to any
desired number When the Parallel Load (PL) input is LOW
information present on the Parallel Data inputs (P0 – P3) is
loaded into the counter and appears on the Q outputs This
operation overrides the counting functions as indicated in
the Mode Select Table A HIGH signal on the CE input inhib-
its counting When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input The direction of counting is determined by
the U D input signal as indicated in the Mode Select Table
CE and U D can be changed with the clock in either state
provided only that the recommended setup and hold times
are observed
RC Truth Table
Inputs
CE TC
LH
HX
XL
TC is generated internally
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
e LOW Pulse
CP
X
X
Output
RC
H
H
State Diagram
Two types of outputs are provided as overflow underflow
indicators The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-
down mode or reaches 9 in the count-up mode The TC
output will then remain HIGH until a state change occurs
whether by counting or presetting or until U D is changed
The TC output should not be used as a clock signal be-
cause it is subject to decoding spikes The TC signal is also
used internally to enable the Ripple Clock (RC) output The
RC output is normally HIGH When CE is LOW and TC is
HIGH the RC output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH again
This feature simplifies the design of multistage counters
For a discussion and illustrations of the various methods of
implementing multistage counters please see the ’F191
data sheet
Mode Select Table
Inputs
PL CE U D
CP
Mode
HL
HL
LX
HH
L L Count Up
H L Count Down
X X Preset (Asyn )
X X No Change (Hold)
TL F 9494 – 5
2
