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74F251A Datasheet

8-Input Multiplexer with TRI-STATE Outputs

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November 1994
54F 74F251A
8-Input Multiplexer with TRI-STATE Outputs
General Description
The ’F251A is a high-speed 8-input digital multiplexer It pro-
vides in one package the ability to select one bit of data
from up to eight sources It can be used as a universal func-
tion generator to generate any logic function of four vari-
ables Both assertion and negation outputs are provided
Features
Y Multifunctional capability
Y On-chip select logic decoding
Y Inverting and non-inverting TRI-STATE outputs
Commercial
74F251APC
74F251ASC (Note 1)
74F251ASJ (Note 1)
Military
54F251ADM (Note 2)
54F251AFM (Note 2)
54F251ALL (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
IEEE IEC
TL F 9504–3
TL F 9504 – 1
TL F 9504 – 2
TL F 9504–5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9504
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F251A Datasheet

8-Input Multiplexer with TRI-STATE Outputs

No Preview Available !

Unit Loading Fan Out
Pin Names
S0 – S2
OE
I0 – I7
Z
Z
Description
Select Inputs
TRI-STATE Output Enable Input (Active LOW)
Multiplexer Inputs
TRI-STATE Multiplexer Output
Complementary TRI-STATE Multiplexer Output
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
b3 mA 24 mA (20 mA)
Functional Description
This device is a logical implementation of a single-pole 8-
position switch with the switch position controlled by the
state of three Select inputs S0 S1 S2 Both assertion and
negation outputs are provided The Output Enable input
(OE) is active LOW When it is activated the logic function
provided at the output is
Z e OE(I0S0S1 S2 a I1S0S1S2 a
I2S0S1S2 a I3S0S1S2 a
I4S0S1S2 a I5S0S1S2 a
I6S0S1S2 a I7S0S1S2)
When the Output Enable is HIGH both outputs are in the
high impedance (High Z) state This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together When the outputs of the TRI-STATE devices are
tied together all but one device must be in the high imped-
ance state to avoid high currents that would exceed the
maximum ratings The Output Enable signals should be de-
signed to ensure there is no overlap in the active LOW por-
tion of the enable voltages
Logic Diagram
Truth Table
Inputs
OE S2 S1
H XX
L LL
L LL
L LH
LL
LH
LH
LH
LH
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
H
L
L
H
H
S0
X
L
H
L
H
L
H
L
H
Outputs
ZZ
ZZ
I0 I0
I1 I1
I2 I2
I3 I3
I4 I4
I5 I5
I6 I6
I7 I7
TL F 9504 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F251A
Description 8-Input Multiplexer with TRI-STATE Outputs
Maker National Semiconductor
Total Page 8 Pages
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