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National Semiconductor Electronic Components Datasheet

74F382 Datasheet

4-Bit Arithmetic Logic Unit

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August 1995
74F382
4-Bit Arithmetic Logic Unit
General Description
The ’F382 performs three arithmetic and three logic opera-
tions on two 4-bit words A and B Two additional Select
input codes force the Function outputs LOW or HIGH An
Overflow output is provided for convenience in twos com-
plement arithmetic A Carry output is provided for ripple ex-
pansion For high-speed expansion using a Carry Look-
ahead Generator refer to the ’F381 data sheet
Features
Y Performs six arithmetic and logic functions
Y Selectable LOW (clear) and HIGH (preset) functions
Y LOW input loading minimizes drive requirements
Y Carry output for ripple expansion
Y Overflow output for twos complement arithmetic
Commercial
74F382PC
74F382SC (Note 1)
74F382SJ (Note 1)
Package
Number
N20A
M20B
M20D
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
IEEE IEC
Connection Diagram
Pin Assignment
for DIP and SOIC
TL F 9529– 6
C1995 National Semiconductor Corporation TL F 9529
TL F 9529–3
TL F 9529 –1
RRD-B30M105 Printed in U S A
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National Semiconductor Electronic Components Datasheet

74F382 Datasheet

4-Bit Arithmetic Logic Unit

No Preview Available !

Unit Loading Fan Out
Pin Names
Description
A0 – A3
B0 – B3
S0 – S2
Cn
Cn a 4
OVR
F0 – F3
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Output
Overflow Output
Function Outputs
74F
UL
HIGH LOW
10 40
10 40
10 10
10 50
50 33 3
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b2 4 mA
20 mA b2 4 mA
20 mA b0 6 mA
20 mA b3 0 mA
b1 mA 20 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
Signals applied to the Select inputs S0 – S2 determine the
mode of operation as indicated in the Function Select Ta-
ble An extensive listing of input and output levels is shown
in the Truth Table The circuit performs the arithmetic func-
tions for either active HIGH or active LOW operands with
output levels in the same convention In the Subtract oper-
ating modes it is necessary to force a carry (HIGH for active
HIGH operands LOW for active LOW operands) into the Cn
input of the least significant package Ripple expansion is
illustrated in Figure 1 The overflow output OVR is the Exclu-
sive-OR of Cn a 3 and Cn a 4 a HIGH signal on OVR
indicates overflow in twos complement operation Typical
delays for Figure 1 are given in Figure 2
Function Select Table
Select
S0 S1
LL
HL
LH
HH
LL
HL
LH
HH
H e HIGH Voltage Level
L e LOW Voltage Level
S2
L
L
L
L
H
H
H
H
Operation
Clear
B Minus A
A Minus B
A Plus B
AZB
AaB
AB
Preset
FIGURE 1 16-Bit Ripply Carry ALU Expansion
Path Segment
Toward
FC
Ai or Bi to Cn a 4
Cn to Cn a 4
Cn to Cn a 4
Cn to F
Cn to Cn a 4 OVR
Total Delay
6 5 ns
6 3 ns
6 3 ns
8 1 ns
27 2 ns
FIGURE 2 16-Bit Delay Tabulation
Output
n a 4 OVR
6 5 ns
6 3 ns
6 3 ns
8 0 ns
27 1 ns
TL F 9529 – 5
2


Part Number 74F382
Description 4-Bit Arithmetic Logic Unit
Maker National Semiconductor
Total Page 8 Pages
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