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National Semiconductor Electronic Components Datasheet

74F563 Datasheet

Octal D-Type Latch

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May 1995
54F 74F563
Octal D-Type Latch with TRI-STATE Outputs
General Description
The ’F563 is a high-speed octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable
(OE) inputs
This device is functionally identical to the ’F573 but has
inverted outputs
Features
Y Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Y Useful as input or output port for microprocessors
Y Functionally identical to ’F573
Commercial
74F563PC
74F563SC (Note 1)
74F563SJ (Note 1)
Military
54F563DM (Note 2)
54F563FM (Note 2)
54F563LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9562 – 3
Unit Loading Fan Out
Pin Names
D0 – D7
LE
OE
O0 – O7
Description
Data Inputs
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
TL F 9562 – 5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9562
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F563 Datasheet

Octal D-Type Latch

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9562–1
Functional Description
The ’F563 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Logic Diagram
TL F 9562 – 2
Function Table
Inputs
Internal Output
OE LE D
Q
O
H XX
H HL
H HH
H LX
L HL
L HH
L LX
X
H
L
NC
H
L
NC
Z
Z
Z
Z
H
L
NC
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
NC e No Change
Function
High Z
High Z
High Z
Latched
Transparent
Transparent
Latched
TL F 9562 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F563
Description Octal D-Type Latch
Maker National Semiconductor
Total Page 8 Pages
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