Description
The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0
Q3)
When the Enable (E) is HIGH and the Clear input (CL) i
Features
- Y Serial-to-parallel capability Y Output from each storage bit available Y Random (addressable) data entry Y Easily expandable Y Active low common clear
Connection Diagram Logic Symbol
Dual-In-Line Package
TL F 9823.
- 1
Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Number J16A
N16E or W16A
VCC e Pin 16 GND e Pin 8
Pin Names
A0 A1 Da Db E CL Q0a.
- Q3a Q0b.
- Q3b.
74LS256 Datasheet
