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National Semiconductor Electronic Components Datasheet

CD4023M Datasheet

Triple 3-Input NAND(NOR) Gate

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February 1988
CD4023M CD4023C Triple 3-Input NAND Gate
CD4025M CD4025C Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement mode transistors All inputs are protected
against static discharge with diodes to VDD and VSS
Features
Y Wide supply voltage range
Y High noise immunity
Y 5V – 10V parametric ratings
Y Low power
3 0V to 15V
0 45 VDD (typ )
Connection Diagrams
CD4023M CD4023C
Dual-In-Line Packages
CD4025M CD4025C
Top View
TL F 5955 – 1
Order Number CD4023 or CD4025
Top View
TL F 5955 – 2
C1995 National Semiconductor Corporation TL F 5955
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

CD4023M Datasheet

Triple 3-Input NAND(NOR) Gate

No Preview Available !

Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range
CD4023M CD4025M
CD4023C CD4025C
VSSb to VDD a0 3V
b55 C to a125 C
b40 C to a85 C
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VDD Range
Lead Temperature
(Soldering 10 seconds)
b65 C to a150 C
700 mW
500 mW
VSS a3 0V to VSS a15V
260 C
DC Electrical Characteristics CD4023M CD4025M
Limits
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C Units
Min Max Min Typ Max Min Max
IL Quiescent Device
Current
VDD e 5 0V
VDD e 10V
0 05 0 001 0 05
0 1 0 001 0 1
3 0 mA
6 0 mA
PD Quiescent Device
VDD e 5 0V
Dissipation Package
VDD e 10V
0 25 0 005 0 25
1 0 0 01 1 0
15 mW
60 mW
VOL Output Voltage
Low Level
VDD e 5 0V VI e VDD IO e 0A
VDD e 10V VI e VDD IO e 0A
0 05
0 0 05
0 05 V
0 05
0 0 05
0 05 V
VOH Output Voltage
High Level
VDD e 5 0V VI e VSS IO e 0A
VDD e 10V VI e VSS IO e 0A
4 95
9 95
4 95 5 0
9 95 10
4 95
9 95
V
V
VNL Noise Immunity
(All Inputs)
VDD e 5 0V VO e 3 6V IO e 0A
VDD e 10V VO e 7 2V IO e 0A
15
30
1 5 2 25
30 45
14
29
V
V
VNH Noise Immunity
(All Inputs)
VDD e 5 0V VO e 0 95V IO e 0A 1 4
VDD e 10V VO e 2 9V IO e 0A
29
1 5 2 25
30 45
15
30
V
V
IDN Output Drive Current
VDD e 5 0V VO e 0 4V VI e VDD 0 5
N-Channel (4025) (Note 2) VDD e 10V VO e 0 5V VI e VDD 1 1
0 40 1 0
09 25
0 28
0 65
mA
mA
IDP Output Drive Current
VDD e 5 0V VO e 2 5V VI e VSS b0 62
P-Channel (4025) (Note 2) VDD e 10V VO e 9 5V VI e VSS b0 62
b0 5 b2 0
b0 5 b1 0
b0 35
b0 35
mA
mA
IDN Output Drive Current
VDD e 5 0V VO e 0 4V VI e VDD 0 31
N-Channel (4023) (Note 2) VDD e 10V VO e 0 5V VI e VDD 0 63
0 25 0 5
05 06
0 175
0 35
mA
mA
IDP Output Drive Current
VDD e 5 0V VO e 2 5V VI e VSS b0 31
P-Channel (4023) (Note 2) VDD e 10V VO e 9 5V VI e VSS b0 75
b0 25 b0 5
b0 6 b1 2
b0 175
b0 4
mA
mA
II Input Current
10 pA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 IDN and IDP are tested one output at a time
2


Part Number CD4023M
Description Triple 3-Input NAND(NOR) Gate
Maker National Semiconductor
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CD4023M Datasheet PDF






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