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National Semiconductor Electronic Components Datasheet

CD4025BM Datasheet

Buffered Triple 3-Input NAND/NOR Gate

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February 1988
CD4023BM CD4023BC
Buffered Triple 3-Input NAND Gate
CD4025BM CD4025BC
Buffered Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement mode transistors They have equal source
and sink current capabilities and conform to standard B se-
ries output drive The devices also have buffered outputs
which improve transfer characteristics by providing very
high gain All inputs are protected against static discharge
with diodes to VDD and VSS
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power TTL
0 45 VDD (typ )
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y 5V – 10V – 15V parametric ratings
Y Symmetrical output characteristics
Y Maximum input leakage 1 mA at 15V over full
temperature range
Connection Diagrams
CD4023BM CD4023BC
Dual-In-Line Package
CD4025BM CD4025BC
Dual-In-Line Package
Top View
TL F 5956 – 1
Order Number CD4023B or CD4025B
Top View
TL F 5956 – 2
C1995 National Semiconductor Corporation TL F 5956
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

CD4025BM Datasheet

Buffered Triple 3-Input NAND/NOR Gate

No Preview Available !

Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temp Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
b0 5 VDC to a18 VDC
b0 5 VDC to VDDa0 5 VDC
b65 C to a150 C
700 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
DC Supply Voltage (VDD)
Input Voltage (VIN)
Operating Temperature Range (TA)
CD4023BM CD4025BM
CD4023BC CD4025BC
5 VDC to 15 VDC
0 VDC to VDD VDC
b55 C to a125 C
b40 C to a85 C
DC Electrical Characteristics CD4023BM CD4025BM (Note 2)
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C Units
Min Typ Min Typ Max Min Max
IDD Quiescent Device Current VDD e 5V
VDD e 10V
VDD e 15V
VOL Low Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
0 25
05
10
0 05
0 05
0 05
0 004
0 005
0 006
0
0
0
0 25
05
10
0 05
0 05
0 05
7 5 mA
15 mA
30 mA
0 05 V
0 05 V
0 05 V
VOH
High Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
4 95
9 95
14 95
4 95
9 95
14 95
5
10
15
4 95
9 95
14 95
V
V
V
VIL Low Level Input Voltage VDDe5V VOe4 5V
l lVDDe10V VOe9 0V IO k1mA
(VDDe15V VOe13 5V
15
30
40
2 15
4 30
6 40
15 V
30 V
40 V
VIH High Level Input Voltage VDDe5V VOe0 5V
35
l lVDDe10V VOe1 0V IO k1mA 7 0
(VDDe15V VOe1 5V
11 0
35 3
70 6
11 0 9
35 V
70 V
11 0 V
IOL Low Level Output Current VDDe5V VO e 0 4V
(Note 3)
VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
0 64 0 51 0 88
16 13 22
42 34 8
0 36 mA
0 90 mA
2 4 mA
IOH High Level Output Current VDD e 5V VO e 4 6V
(Note 3)
VDD e 10V VO e 9 5V
VDD e 15V VO e 13 5V
b0 64
b1 6
b4 2
b0 51 b0 88
b1 3 b2 2
b3 4 b8
b0 36
b0 90
b2 4
mA
mA
mA
IIN Input Current
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b0 10
0 10
b10b5 b0 10
10b5 0 10
b1 0 mA
1 0 mA
Schematic Diagram
CD4023BC CD4023BM
Device Shown
All Inputs Protected
by Standard CMOS Input
Protection Circuit
TL F 5956 – 3
2


Part Number CD4025BM
Description Buffered Triple 3-Input NAND/NOR Gate
Maker National Semiconductor
PDF Download

CD4025BM Datasheet PDF






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