CGS74C802 driver equivalent, low skew pll 1-to-8 cmos clock driver.
operating at high frequencies utilizing a phase lock loop. The phase lock loop allows for outputs to lock-on to either S.
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These minimum skew clock drivers are designed for Clock Generation and Support (CGS) applications operating at high frequencies utilizing a phase lock loop. The phase lock loop allows for outputs to lock-on to either SyncLO or SyncL1 inputs,.
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