s s s s s s 12-bit settling (0.01%)
  – 17ns Low noise
  – 42µVrms Isolation
  – 80dB @ 10MHz 110MHz -3dB bandwidth (Av = +2) L.

s s s s s Functional Diagram A1 0 0 1 1 A0 0 1 0 1 OUT A B C D Pinout DIP & SOIC ECL Mode - DREF = open TTL Mode - DR.

The CLC533 is a high-speed 4:1 multiplexer employing active input and output stages. The CLC533 also employs a closed-loop design which dramatically improves accuracy over conventional analog multiplexer circuits. This monolithic device is constructe.

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