* complementary outputs from each flip-flop Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of
DM54175
National Semiconductor
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Hex/quad d flip-flops.
54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear June 1989 54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-F.
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