Description
These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) version
Features
- complementary outputs from each flip-flop
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output
Features
Y 174 contains six flip-flops with single-rail outputs Y 175 c.
DM54175 Datasheet
