Datasheet4U Logo Datasheet4U.com

DM5474 - Dual Positive-Edge-Triggered D Flip-Flops

General Description

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time

Key Features

  • Y Alternate Military Aerospace device (5474) is available Contact a National Semiconductor Sales Office Distributor for specific.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DM54141 BCD / DECIMAL DECODERS / DRIVERS MSI
DM54155 Dual 2-Line to 4-Line Decoders/Demultiplexers ETC
DM5441A BCD / DECIMAL DECODERS / DRIVERS MSI
DM5446A BCD/7-Segment Decoder/Driver MSI
DM5447A BCD/7-Segment Decoder/Driver MSI

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
DM5470 AND Gated Positive Edge Triggered J-K Flip-Flop
DM5476 Dual Master-Slave J-K Flip-Flops
DM5400 Quad 2-Input NAND Gates
DM5401 Quad 2-Input NAND Gates with Open-Collector Outputs
DM5402 Quad 2-Input NOR Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset