DM54LS191 Datasheet, National Semiconductor

Y Counts 8-4-2-1 BCD or binary Y Single down up count control line Y Count enable control input Y Ripple clock output for cascading Y Asynchronously presettable with load.

Y Average propagation delay 20 ns Y Typical clock frequency 25 MHz Y Typical power dissipation 100 mW Connection Diagra.