DM54LS73A Datasheet - National Semiconductor

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM54LS73A General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negat.

DM54LS73A Datasheet (139.87 KB)

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DM54LS73A

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National Semiconductor

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139.87 KB

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Dual negative-edge-triggered master-slave j-k flip-flops.
DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual.

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DM54LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops National Semiconductor

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DM54LS73A General Description

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