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DM54LS73A Datasheet

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

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June 1989
DM54LS73A DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse The data on the J
and K inputs is allowed to change while the clock is high or
low without affecting the outputs as long as setup and hold
times are not violated A low logic level on the clear input
will reset the outputs regardless of the levels of the other
inputs
Connection Diagram
Dual-In-Line Package
www.DataSheet4U.com
TL F 6372 – 1
Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN
See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs
Outputs
CLR CLK J K
Q
Q
L
X
XX
L
H
vH
L L Q0
Q0
H v HL H L
H v LH L H
H v HH
Toggle
H
H
X X Q0
Q0
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
v e Negative going edge of pulse
Q0 e The output logic level before the indicated input conditions were es-
tablished
Toggle e Each output changes to the complement of its previous level on
each falling edge of the clock pulse
C1995 National Semiconductor Corporation TL F 6372
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

DM54LS73A Datasheet

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

No Preview Available !

Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54LS73A
Min Nom Max
VCC
VIH
VIL
IOH
IOL
fCLK
fCLK
tW
Supply Voltage
45 5 55
High Level Input Voltage
2
Low Level Input Voltage
07
High Level Output Current
b0 4
Low Level Output Current
4
Clock Frequency (Note 2)
0
30
Clock Frequency (Note 3)
0
25
Pulse Width
(Note 2)
Clock High
Preset Low
20
25
Clear Low
25
tW
Pulse Width
Clock High
25
(Note 3)
Preset Low
30
Clear Low
30
tSU Setup Time (Notes 1 and 2)
20v
tSU Setup Time (Notes 1 and 3)
25v
tH Hold Time (Notes 1 and 2)
0v
tH Hold Time (Notes 1 and 3)
5v
TA
Free Air Operating Temperature
b55
vNote 1 The symbol ( ) indicates the falling edge of the clock pulse is used for reference
Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
125
DM74LS73A
Min Nom Max
4 75 5 5 25
2
08
b0 4
8
0 30
0 25
20
25
25
25
30
30
20v
25v
0v
5v
0 70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
ns
C
2


Part Number DM54LS73A
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
Maker National Semiconductor
Total Page 6 Pages
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