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National Semiconductor Electronic Components Datasheet

DM74LS90N Datasheet

Decade and Binary Counters

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August 1986
Revised March 2000
DM74LS90
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nine’s complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetri-
cal divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the QD output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.
Features
s Typical power dissipation 45 mW
s Count frequency 42 MHz
Ordering Code:
Order Number Package Number
Package Description
DM74LS90M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Reset/Count Truth Table
R0(1)
H
H
X
X
L
L
X
Reset Inputs
R0(2) R9(1)
H
L
H
X
X
H
L
X
X
L
X
X
L
L
R9(2)
X
L
H
L
X
L
X
Output
QD QC QB QA
LLLL
LLLL
HL LH
COUNT
COUNT
COUNT
COUNT
© 2000 Fairchild Semiconductor Corporation DS006381
www.fairchildsemi.com


National Semiconductor Electronic Components Datasheet

DM74LS90N Datasheet

Decade and Binary Counters

No Preview Available !

Function Tables
BCD Count Sequence (Note 1)
Count
Output
QD
QC
QB
QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
Count
0
1
2
3
4
5
6
7
8
9
Bi-Quinary (5-2) (Note 2)
Output
QA
QD
QC
QB
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is connected to input A for bi-quinary count.
Note 3: Output QA is connected to input B.
Logic Diagram
The J and K inputs shown without connection are for reference only and
are functionally at a high level.
www.fairchildsemi.com
2


Part Number DM74LS90N
Description Decade and Binary Counters
Maker National Semiconductor
PDF Download

DM74LS90N Datasheet PDF






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