Description
These circuits are synchronous edge-sensitive fully-programmable 4-bit counters The counters feature both conventional totem-pole and TRI-STATE outputs such that when the outputs are in the high impedance mode they can be used to enter data from the bus lines In addition the clear input operates com
Features
- Y Y Y Y Y
Typical clock frequency 35 MHz TRI-STATE outputs Fully independent clear Synchronous loading Cascading circuitry provided internally
Connection Diagram
Dual-In-Line Package
TL F 6588.
- 1
Order Number DM7556J or DM8556N See NS Package Number J16A or N16A
Function Table
Control Inputs LOAD H H H H L H H CE X X X X H L L CLK X X L L OD L H L H L L H Reset H H L L L L L I OA L Z QA0 Z a Z I O Ports I OB I OC I OD L Z QD0 Z d Z QA L L QA0 QA0 A Active Outputs QB QC QD L L QD0 Q.
DM7556 Datasheet
