16-Lead Plastic TSSOP
θJA = 155˚C/W
NSC Package Drawing
92 Units Per Rail
2.5k Units Per Reel
BOOST (Pin 1): Supply rail for the high-side FET gate drive.
The voltage should be at least one gate threshold above the
regulator input voltage to properly turn on the high-side FET.
HG (Pin 2): Gate drive for the high-side N-channel FET. This
signal is interlocked with LG to avoid shoot-through.
SW/CSH (Pin 3): Return path for the high-side FET driver
and top Kelvin sense point for the load current. Connect this
pin as close as possible to the drain of the low-side FET with
a separate trace. Also used along with CSL for zero crossing
CSL (Pin 4): Bottom sense point for the load current. Con-
nect this as close as possible to the source of the low-side
FET with a separate trace.
ILIM (Pin 5): Current limit threshold setting. This pin sources
a fixed 20 µA current. A resistor of appropriate value should
be connected between this pin and the drain of the low-side
FPWM (Pin 6): Control mode select. An open circuit at this
pin allows the IC to operate in skip mode at light loads. A
logic low or connection to ground forces PWM operation at
all times. This pin should not be pulled up to any voltage
SNS (Pin 7): Output voltage sense pin. Connect this pin as
close as possible to the positive terminal of the output ca-
pacitor with a separate trace. This pin connects to an internal
FET that discharges the output capacitor during shutdown.
FREQ/SYNC (Pin 8): Switching frequency select pin and
input for external clock. Connect a resistor from this pin to
ground to determine switching frequency. Alternatively, a
logic level clock signal between 200 kHz and 1.5 MHz can be
applied to this pin through a 100 pF DC blocking capacitor to
set the switching frequency.
TRACK (Pin 9): Tracking pin. To force the output of the
LM3495 to track another power supply, connect a resistor
divider (smaller than 10 kΩ for better precision) from the
output of the other supply directly to this pin. When not used,
this pin should be connected directly to the VLIN5 pin.
FB (Pin 10): Feedback pin. Connecting a resistor divider
from the output voltage to this pin sets the DC level of the
COMP/SD (Pin 11): Output of the error amplifier. The volt-
age level on this pin is compared with an internally gener-
ated ramp signal to determine the duty cycle. This pin is
necessary for compensating the control loop. This pin must
be left floating for the converter to regulate the output voltage
in steady state. Forcing this pin below 0.3V shuts down the
SGND (Pin 12): Signal ground. Ground connection for the
low power analog circuitry. Connect this pin to the PGND pin
with a separate trace.
VIN (Pin 13): Input voltage. Input to an internal 4.7V linear
regulator. Bypass this pin with a minimum 1 µF ceramic
VLIN5 (Pin 14): Output of the internal 4.7V linear regulator.
Provides power to the high-side bootstrap and low-side
driver. Bypass this pin with a 2.2 µF ceramic capacitor to
LG (Pin 15): Gate drive for the low-side N-channel FET. This
signal is interlocked with HG to avoid shoot-through.
PGND (Pin 16): Ground connection for the power circuitry.
Connect to the source of the low-side FET and the output
capacitor with heavy traces or a copper plane.