LM4312 Datasheet | National Semiconductor

LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Dithering and Look Up Table May 12, 2008 LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Dithering and Look Up Table General Description The LM4312 is a MPL-2 Serializer (SER) that accepts a 24or 18-RGB interface and serializes this wide bus to 3 differential signals. The optional Dithering feature can reduce 24bit RGB to 18-bit RGB. The optional Look Up Table (Three X 256 X 8 bit RAM) is provided for independent color correction. 18-bit Bufferless displays from QVGA (320 x 240) up to >VGA (640 x 480) pixels are supported. The interconnect is reduced from 28 LVCMOS signals (RGB888+V+H+DE+PCLK) to only 3 active differential signals (DD0P/M, DCP/M, DD1P/M) with the LM4312 Serializer and panion LM4310 Deserializer easing flex interconnect design, size constraints and cost. The LM4312 SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial MPL-2 levels for transmission over a flex cable and PCB traces to the DES located in the display module. When in Power_Down, the SER is put to sleep and draws less than 10μA. The SER can be powered down by stopping the PCLK or by asserting its PD- input pin. The LM4312 implements the physical layer of the MPL-2 Interface and Features robust mon-mode noise rejection. Features - RGB Display Interface to >640 x 480 (VGA) Resolution - 24 or 18-bit RGB Transport - 24- to- 18-bit RGB Dithering option - Look Up Table option for independent color correction option - Robust MPL-2 Differential SLVS Interface - SPI Interface for configuration / control and LUT options - Low Power Consumption & SLEEP state - Auto Power Down on STOP PCLK - Automatically generates frame sequence bits for resync upon data or clock error - Odd Parity Generation System Benefits - Dithered Data Reduction - Independent RGB Color...