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New Japan Radio

NJU26126 Datasheet Preview

NJU26126 Datasheet

Digital Signal Processor

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NJU26126
Digital Signal Processor
General Description
The NJU26126 is a high performance 24-bit digital signal processor.
The NJU26126 provides L/R channel independent 10bands PEQ, Low/High
bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio
Delay, eala & eala Rebirth of NJRC Original Sound Enhancement, Dynamic
Bass Boost, two systems Limiter, and 5.1 channel output function. These kinds
of sound functions are suitable for TV, mini-component, CD radio-cassette,
Sound bar and speakers system.
Package
NJU26126VC2
FEATURES
- Software
NJRC Original Sound Enhancement (eala, eala Rebirth, Dynamic Bass Boost)
HPF, LPF, Center/Sub woofer and Surround output function
10bands PEQ (Parametrical Equalizer) : L/R channel independent operation
DRC (Dynamic Range Compression) : 2-bands independent operation (FIR filter adoption)
Tone Control (Bass / Treble)
Limiter (SDO0 / SDO1)
Lip sync Audio Delay (fs=48kHz : Max. 22msec)
Signal level detector
Watchdog Clock Output
- Hardware
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
Digital Audio Interface
: 3 Input ports / 3 Output ports
Digital Audio Format
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
Host Interface
: I2C bus (Fast-mode/400kbps)
Power Supply
: 3.3V
Input terminal
: 5V Input tolerant
Package
: SSOP24-C2 (Pb-Free)
Ver.2010-08-19
-1-




New Japan Radio

NJU26126 Datasheet Preview

NJU26126 Datasheet

Digital Signal Processor

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NJU26126
Function Block Diagram
SCL
SDA
I2C INTERFACE
RESETb
MCK
CLKOUT
CLK
SLAVEb
TIMING
GENERATOR /
PLL
Internal Pow er
(1.8V)
VREGO
External
Low -ESR
Capacitors
Required
Built-in LDO
1.8V level terminal
24Bit Fixed-point DSP Core
PROGRAM
CONTROL
ALU
24Bit x 24Bit
MULTIPLIER
ADDRESS GENERATION UNIT
DATA RAM
FIRMWARE
ROM
SERIAL AUDIO
INTERFACE
SDI0-2
SDO0-2
BCK
LR
GPIO
INTERFACE
WDC
PROC
AD1
DSP Block Diagram
Fig. 1 NJU26126 Block Diagram
NJU26126 Block Diagram
SDI0
SDI1
SDI2
Signal Level
Detector
(No Signal Counter)
Input
Trimmer
Delay
(22ms)
PEQ
(10band/9band+HPF)
SW1
Tone Control
(0.5dB step)
TDheelaDyelayprocessingpIonspitiuotn/cSaDnObe0e/xScDlusOiv1e/lySDO2
Selectedfrom eitherof Input/SDO0/SDO1/SDO2.
eala /
eala Rebirth
SW5(DRC enable/disable)
Dynamic
SW2 Bass Boost SW3
Exec Volume
(0~-96dB,mute, 0.25dB step)
L/R trimmer
(0~-96dB,mute, 0.5dB step)
EXEC Output
HPF
SW
LPF
DRC(HPF)
SW
DRC(LPF) SW
SW
SW
HPF Output
LPF Output
SW4 (DRC Xover enable/disable)
HPDFR/LCPF eOxFecFuting eHvPenFi/f DLRPCFisdisabled. す。
WDheRnCDRMCixaenrdXOVEDRRoCpt(ioLnPaFre)onlyDeRnaCbledE, DnaRbCleMixercanbe used.
I(f Hyoowuesveenrd, itFisilXtelimOrciVtoeeEdffRtioc ie2no0tp0,0ytioHouzncoarnleEusnssae.)bthleeXOVERfrequ使enciesotherthanthepresetfrequency.
DRC Mixer
SW SW
C/SW Mixer
eala /
eala Rebirth
SW2
Surround
Signal
Generator
PROC Output
Surround Output
C/SW Output
PROC Output
HPF Output
LPF Output
EXEC Output
C/SW Output
Surround Output
SDO0/1/2
Source Select
Delay
(22ms)
SDO0
SDO0
Limiter
Delay
(22ms)
Delay
(22ms)
SDO1
SDO2
Master Volume
(+24dB~-96dB,mute, 0.25dB step)
&
Channel Trimmer
(0dB~-96dB,mute, 0.5dB step)
SDO1
SDO2
Limiter
Delay処理位置は、
ThIenpDuetla/ySpDroOce0s/sSinDgOpo1s/itSionDcOa2nbeexclusivelyから排他的に選択可能です。
Selectedfrom eitherof Input/SDO0/SDO1/SDO2.
SDO0
SW6
SDO1
SW7
SDO2
Fig. 2 NJU26126 Function Diagram
-2-
Ver.2010-08-19


Part Number NJU26126
Description Digital Signal Processor
Maker New Japan Radio
Total Page 18 Pages
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