Datasheet4U Logo Datasheet4U.com

P5504EDG - P-Channel Logic Level Enhancement

Download the P5504EDG datasheet PDF. This datasheet also covers the P5504EDG_Niko variant, as both devices belong to the same p-channel logic level enhancement family and are provided as variant models within a single manufacturer datasheet.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (P5504EDG_Niko-Sem.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number P5504EDG
Manufacturer NIKO-SEM
File Size 409.47 KB
Description P-Channel Logic Level Enhancement
Datasheet download datasheet P5504EDG Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NIKO-SEM P-Channel Enhancement Mode Field Effect Transistor P5504EDG TO-252 Halogen-Free & Lead-Free D PRODUCT SUMMARY V(BR)DSS -40V RDS(ON) 55mΩ ID -21A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -40 ±20 -21 -13 -39 41 16 -55 to 150 UNITS V V TC = 25 °C TC = 100 °C ID IDM A TC = 25 °C TC = 100 °C PD Tj, Tstg W °C Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 SYMBOL RθJC RθJA TYPICAL MAXIMUM 3 75 UNITS °C / W °C / W Pulse width limited by maximum junction temperature.