MS81V04166 Datasheet | OKI Electric

PEDS81V04166-01 1 Semiconductor MS81V04166 Dual FIFO (262,214 Words × 8 Bits) × 2 This version: Dec. 2001 Preliminary GENERAL DESCRIPTION The MS81V04166 is a single-chip 4Mb FIFO functionally posed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation. .. The read clock of each of the 2Mb FIFO memories is connected in mon, and the clocks are provided independently of each of the FIFO memories. The MS81V04166 functionally patible with Oki’s 2Mb FIFO memory (MSM51V8222A), can be used as a ×16 configuration FIFO. The MS81V04166 is a field memory for wide or low end use in general modity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. The MS81V04166 provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MS81V04166 provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V04166 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V04166’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial...