2, 4 and 8-Channel
The CM1231−02SO is specifically designed for next generation
deep submicron ASIC protection. These devices are ideal for
protecting systems with high data and clock rates and for circuits
requiring low capacitive loading such as USB 2.0.
The CM1231−02SO incorporates dual stage ESD architecture
which offers dramatically higher system level ESD protection
compared with traditional single clamp designs. In addition, the
CM1231−02SO provides a controlled filter roll−off for even greater
spurious EMI suppression and signal integrity.
The CM1231−02SO protects against ESD pulses up to ±12 kV
contact on the “OUT” pins per the IEC 61000−4−2 standard.
The device also features easily routed “pass−through” differential
pinouts in a 6−lead SOT23 package.
• Two Channels of ESD Protection
• Exceeds ESD Protection to IEC61000−4−2 Level 4:
• ±12 kV Contact Discharge (OUT Pins)
• Two−Stage Matched Clamp Architecture
• Matching−of−Series Resistor (R) of ±10 mW Typical
• Flow−Through Routing for High−Speed Signal Integrity
• Differential Channel Input Capacitance Matching of 0.02 pF Typical
• Improved Powered ASIC Latchup Protection
• Dramatic Improvement in ESD Protection vs. Best in Class
Single−Stage Diode Arrays
• 40% Reduction in Peak Clamping Voltage
• 40% Reduction in Peak Residual Current
• Withstands over 1000 ESD Strikes*
• Available in a SOT23−6 Package
• These Devices are Pb−Free and are RoHS Compliant
• USB Devices Data Port Protection
• General High−Speed Data Line ESD Protection
D312 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
CM1231−02SO SOT23−6 3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
*Standard test condition is IEC61000−4−2 level 4 test circuit with each (AOUT/BOUT) pin subjected to ±12 kV contact discharge for 1000 pulses.
Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 4
Publication Order Number: