
	ON Semiconductor Electronic Components Datasheet

FAN3121 Datasheet

Low-Side Gate Driver

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FAN3121 / FAN3122

Single 9-A High-Speed, Low-Side Gate Driver

Features

! Industry-Standard Pin-out with Enable Input

! 4.5-V to 18-V Operating Range

! 11.4 A Peak Sink at VDD = 12 V

! 9.7-A Sink / 7.1-A Source at VOUT = 6 V

! Inverting Configuration (FAN3121) and

Non-Inverting Configuration (FAN3122)

! Internal Resistors Turn Driver Off If No Inputs

! 23-ns / 19-ns Typical Rise/Fall Times (10 nF Load)

! 18 ns to 23 ns Typical Propagation Delay Time

! Choice of TTL or CMOS Input Thresholds

! MillerDrive™ Technology

! Available in Thermally Enhanced 3x3 mm 8-Lead

MLP or 8-Lead SOIC Package (Pb-Free Finish)

! Rated from –40°C to +125°C

! Automotive Qualified to AEC-Q100 (F085 Versions)

Applications

! Synchronous Rectifier Circuits

! High-Efficiency MOSFET Switching

! Switch-Mode Power Supplies

! DC-to-DC Converters

! Motor Control

! Automotive-Qualified Systems (F085 Versions)

Description

The FAN3121 and FAN3122 MOSFET drivers are

designed to drive N-channel enhancement MOSFETs in

low-side switching applications by providing high peak

current pulses. The drivers are available with either TTL

input thresholds (FAN312xT) or VDD-proportional CMOS

input thresholds (FAN312xC). Internal circuitry provides

an under-voltage lockout function by holding the output

low until the supply voltage is within the operating range.

FAN312x drivers incorporate the MillerDrive™

architecture for the final output stage. This bipolar /

MOSFET combination provides the highest peak current

during the Miller plateau stage of the MOSFET turn-on /

turn-off process.

The FAN3121 and FAN3122 drivers implement an

enable function on pin 3 (EN), previously unused in the

industry-standard pin-out. The pin is internally pulled up

to VDD for active HIGH logic and can be left open for

standard operation.

The commercial FAN3121/22 is available in a 3x3 mm

8-lead thermally-enhanced MLP package or an 8-lead

SOIC package. The AEC-Q100 automotive-qualified

versions are available in the 8-lead SOIC package.

VDD 1

IN 2

EN 3

GND 4

8 VDD

7 OUT

6 OUT

5 GND

Figure 1. FAN3121 Pin Configuration

VDD 1

IN 2

EN 3

GND 4

8 VDD

7 OUT

6 OUT

5 GND

Figure 2. FAN3122 Pin Configuration

October-2017, Rev. 2

Publication Order Number:

FAN3122T-F085/D


	ON Semiconductor Electronic Components Datasheet

FAN3121 Datasheet

Low-Side Gate Driver

No Preview Available !

Ordering Information

Part Number

Logic

FAN3121CMPX

FAN3121CMX

FAN3121CMX-F085(1)

FAN3121TMPX

FAN3121TMX

Inverting

Channels +

Enable

FAN3121TMX-F085 (1)

FAN3122CMPX

FAN3122CMX

FAN3122CMX-F085(1)

FAN3122TMPX

FAN3122TMX

Non-Inverting

Channels +

Enable

FAN3122TMX-F085(1)

Note:

1. Qualified to AEC-Q100.

Package Outlines

Input

Threshold

CMOS

TTL

CMOS

TTL

Package

3x3 mm MLP-8

SOIC-8

3x3 mm MLP-8

SOIC-8

3x3 mm MLP-8

SOIC-8

3x3 mm MLP-8

SOIC-8

Packing

Method

Tape & Reel

Quantity

per Reel

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

Figure 3. 3x3 mm MLP-8 (Top View)

Figure 4. SOIC-8 (Top View)

Thermal Characteristics(2)

Package

(3)

(4)

(5)

(6)

(7)

Units

8-Lead 3x3 mm Molded Leadless Package (MLP)

1.2 64 42 2.8 0.7 °C/W

8-Pin Small Outline Integrated Circuit (SOIC)

38 29 87 41 2.3 °C/W

Notes:

2. Estimates derived from thermal simulation; actual values depend on the application.

3. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

(including any thermal pad) that are typically soldered to a PCB.

4. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,

assuming it is held at a uniform temperature by a top-side heatsink.

5. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,

and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards

JESD51-2, JESD51-5, and JESD51-7, as appropriate.

6. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction

temperature and an application circuit board reference point for the thermal environment defined in Note 5. For

the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and

protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB

copper adjacent to pin 6.

7. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction

temperature and the center of the top of the package for the thermal environment defined in Note 5.

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FAN3121 Datasheet

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