Description
These Dual P-Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology.
Features
- -25 V, -0.12 A continuous, -0.5 A Peak. RDS(ON) = 13 Ω @ VGS= -2.7 V RDS(ON) = 10 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model
Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET. SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS
Drain-Source Voltage
VG.
FDC6302P-ONSemiconductor.pdf
