FDC6320C Datasheet PDF - ON Semiconductor Dual N & P Channel Digital FET Specs

FDC6320C - Dual N & P Channel Digital FET

Datasheet Summary

Description

These dual N & P Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Features

N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 43 52 61 Absolute Maximum Ratings TA = 25oC unless other wise noted Symbol Parameter N-Channel VDSS, VCC VGSS, VIN ID, IO Drain-Source Vo.

Datasheet Details

Part number	FDC6320C
Manufacturer	ON Semiconductor
File Size	490.96 KB
Description	Dual N & P Channel Digital FET
Datasheet	FDC6320C Datasheet
Additional preview pages of the FDC6320C datasheet.

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Full PDF Text Transcription

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FDC6320C Dual N & P Channel , Digital FET General Description These dual N & P Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. Features N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits.

Published: Mar 22, 2020 |