Datasheet Summary
Digital FET, Dual N & P Channel
General Description These dual N & P- Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology, this very high density process is especially tailored to minimize on- state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
Features
- N- Ch 0.22 A, 0.25 V
- RDS(ON) = 4.0 W @ VGS = 4.5 V
- RDS(ON) = 5.0 W @ VGS =...
