Description
These dual N & P-Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology.
This very high density process is especially tailored to minimizeon-state resistance.
Features
- N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V, RDS(ON) = 5.0 Ω @ VGS= 2.7 V. P-Ch -0.41 A,-25V, RDS(ON) = 1.1 Ω @ VGS= -4.5V, RDS(ON) = 1.5 Ω @ VGS= -2.7V. Very small package outline SC70-6.
Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). SC70-6
SOT-23
SuperSOTTM-6
SOT-8
SO-8
SOIC-14
S2 G2 D1
pin 1
SC70-6 Mark: .22
D2 G1 S1
16
Q1
25
Q2
34
Absolute Maximum Ratings TA = 25.