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  ON Semiconductor Electronic Components Datasheet  

MC100E210 Datasheet

Differential Fanout Buffer

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MC100E210
5V ECL Dual 1:4, 1:5
Differential Fanout Buffer
The MC100E210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a parttopart skew down to an outputtooutput skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 1020 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 1020 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
For more information on using PECL, designers should refer to
Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
Features
Dual Differential Fanout Buffers
200 ps ParttoPart Skew
50 ps Typical OutputtoOutput Skew
Low Voltage ECL/PECL Compatible
The 100 Series Contains Temperature Compensation
28lead PLCC Packaging
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = 4.2 V to 5.7 V
Internal Input 75 KW Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
ESD Protection: Human Body Model; >2 KV,
Machine Model; >200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 179 devices
These are PbFree Devices
http://onsemi.com
MARKING
DIAGRAM
1 28
PLCC28
FN SUFFIX
CASE 776
MC100E210FNG
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100E210FNG
PLCC28 37 Units / Rail
(PbFree)
MC100E210FNR2G PLCC28 500 Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 3
1
Publication Order Number:
MC100E210/D


  ON Semiconductor Electronic Components Datasheet  

MC100E210 Datasheet

Differential Fanout Buffer

No Preview Available !

MC100E210
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2
25 24 23 22 21 20 19
VEE 26
18
Qa3
VBB 27
17 Qa3
CLKa 28
VCC 1
CLKa 2
28Lead PLCC
(Top View)
16 Qb0
15 VCCO
14 Qb0
CLKb 3
13 Qb1
CLKb 4
12 Qb1
5 6 7 8 9 10 11
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2
cWoanrnneincgte:dAtlloVPCoCw, eVrCSCuOp,palnydtoVgEuEaprainnstemeupsrtobpeereoxpteerrnaatilolyn.
PIN DESCRIPTION
PIN
CLKa, CLKb
CLKa, CLKb
Qa0:3, Qb0:4
Qa0:3, Qb0:4
VBB
VCC, VCCO
VEE
FUNCTION
ECL Differential Input Pairs
ECL Differential Input Pairs
ECL Differential Outputs
ECL Differential Outputs
Reference Output Voltage
Positive Supply
Negative Supply
CLKa
CLKa
CLKb
CLKb
VBB
LOGIC SYMBOL
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
MAXIMUM RATINGS
Symbol
Parameter
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (JunctiontoAmbient)
qJC Thermal Resistance (JunctiontoCase)
VEE
PECL Operating Range
NECL Operating Range
Condition 1
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
0 LFPM
500 LFPM
Standard Board
Condition 2
VI  VCC
VI  VEE
28 PLCC
28 PLCC
28 PLCC
Rating
8
8
6
6
50
100
± 0.5
0 to +85
65 to +150
63.5
43.5
22 to 26
4.2 to 5.7
5.7 to 4.2
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
V
V
Tsol Wave Solder
<2 to 3 sec @ 248°C
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
2


Part Number MC100E210
Description Differential Fanout Buffer
Maker ON Semiconductor
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MC100E210 Datasheet PDF






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