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  ON Semiconductor Electronic Components Datasheet  

MC100E336 Datasheet

5V ECL 3Bit Registered Bus Transceiver

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MC10E336, MC100E336
5VĄECL 3ĆBit Registered
Bus Transceiver
The MC10E/MC100E336 contains three bus transceivers with both
transmit and receive registers. The bus outputs (BUS0–BUS2) are
specified for driving a 25 bus; the receive outputs (Q0 – Q2) are
specified for 50 . The bus outputs feature a normal HIGH level (VOH)
and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the
output emitter-follower is “off”, presenting a high impedance to the bus.
The bus outputs also feature edge slow-down capacitors.
The Transmit Enable pins (TEN) control whether current data is
held in the transmit register, or new data is loaded from the A/B inputs.
A LOW on both of the Bus Enable inputs (BUSEN), when clocked
through the register, disables the bus outputs to –2.0 V.
The receiver section clocks bus data into the receive registers, after
gating with the Receive Enable (RXEN) input.
All registers are clocked by a positive transition of CLK1 or CLK2
(or both).
Additional leadframe grounding is provided through the Ground
pins (GND) which should be connected to 0 V. The GND pins are not
electrically connected to the chip.
The 100 Series contains temperature compensation.
25 Cutoff Bus Outputs
50 Receiver Outputs
Transmit and Receive Registers
1500 ps Max. Clock to Bus
1000 ps Max. Clock to Q
Bus Outputs Feature Internal Edge Slow-Down Capacitors
Additional Package Ground Pins
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE= –4.2 V to –5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 1 KV HBM, > 75 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 430 devices
http://onsemi.com
MARKING
DIAGRAMS
MC10E336FN
AWLYYWW
PLCC–28
FN SUFFIX
CASE 776
28 1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
MC100E336FN
AWLYYWW
28 1
ORDERING INFORMATION
Device
Package
Shipping
MC10E336FN
PLCC–28 37 Units/Rail
MC10E336FNR2 PLCC–28 500 Units/Reel
MC100E336FN
PLCC–28 37 Units/Rail
MC100E336FNR2 PLCC–28 500 Units/Reel
© Semiconductor Components Industries, LLC, 2000
October, 2000 – Rev. 3
1
Publication Order Number:
MC10E336/D


  ON Semiconductor Electronic Components Datasheet  

MC100E336 Datasheet

5V ECL 3Bit Registered Bus Transceiver

No Preview Available !

MC10E336, MC100E336
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
TEN2 TEN1 B2
25 24 23
BUSEN1 26
A2 NC VCCO Q2
22 21 20 19
18
GND
BUSEN2 27
17 BUS2
RXEN 28
16 VCC
VEE 1
CLK1 2
Pinout: 28-Lead PLCC
(Top View)
15 Q1
14 VCCO
CLK2 3
13 BUS1
A0 4
12 GND
5 6 7 8 9 10 11
B0 A1 B1 VCCO BUS0 GND Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
TEN1, TEN2
A0–A2
B0–B2
Q0–Q1
BUSEN1, BUSEN2
BUS0–BUS2
RXEN
CLK1, CLK2
VCC, VCCO
VEE
GND
NC
FUNCTION
ECL Transit Enable
ECL Data Inputs A
ECL Data Inputs B
ECL Output
ECL Bus Enables
ECL Bus Outputs
ECL Receive Enable
ECL Clock Input
Positive Supply
Negative Supply
Ground
No Connect
AB00
AB11
AB22
TEN1
TEN2
RXEN
BUSEN1
BUSEN2
CLK1
CLK2
LOGIC DIAGRAM
0 DQ
1
0 DQ
1
0 DQ
1
25 W CUTOFF BUS0
D
Q
50 W Q0
25 W CUTOFF
BUS1
D 50 W
Q Q1
25 W CUTOFF
BUS2
D 50 W
Q Q2
DQ
http://onsemi.com
2


Part Number MC100E336
Description 5V ECL 3Bit Registered Bus Transceiver
Maker ON Semiconductor
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