MC100E445 Datasheet | onsemi

Description The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to http://onsemi. 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc. PLCC- 28 FN SUFFIX Two selectable serial inputs provide a loopback capability for testing CASE 776 purposes when the device is used in conjunction with the E446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles MARKING DIAGRAM- shifts the start bit for conversion from Qn to Qn- 1. For each additional 1 28 shift required an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to “swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn- 1 output (see Timing Diagram B). MCxxx E445FNG The MODE input is used to select the conversion mode of the device. AWLYYWW With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion xxx = 10 or 100 scheme using two E445’s. When cascaded in an 8-bit conversion scheme A = Assembly Location the devices will not operate at the 2.0 Gb/s data rate of a single device. WL = Wafer Lot Refer to the applications section of this data sheet for more information on YY = Year cascading the E445. WW = Work Week Upon power-up the internal flip-flops will attain a random state. To G = Pb- Free Package synchronize multiple E445’s in a system the master reset must be asserted. The VBB pin, an internally generated voltage supply, is available to this - For additional marking information, refer to device only. For...