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MC100EP131 - ECL Quad D Flip-Flop

MC100EP131 Description

3.3 V/5 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock MC10EP131, MC100EP131 .
The MC10/100EP131 is a Quad Master. slaved D flip. flop with common set and separate resets.

MC100EP131 Features

* 460 ps Typical Propagation Delay
* Maximum Frequency > 3 GHz Typical
* Differential Individual and Common Clocks
* Individual Asynchronous Resets
* Asynchronous Set
* PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
* NECL Mode

MC100EP131 Applications

* requiring the fastest AC performance available. Each flip
* flop may be clocked separately by holding Common Clock (CC) LOW and CC HIGH, then using the differential Clock Enable inputs for clocking (C0
* 3, C0
* 3). Common clocking is achieved by holding the differential inputs C0

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ECL Quad Flip-Flop ON Semiconductor
ON Semiconductor MC100EP131-like datasheet