MC10E137 Datasheet | onsemi

5 V ECL 8‐Bit Ripple Counter Description The MC10E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLin PS™ output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device’s flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 Features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter bees disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to bee enabled on the next transition of the CLK. If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to pensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to bee saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused...