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  ON Semiconductor Electronic Components Datasheet  

MC10E154 Datasheet

5-BIT 2:1 MUX-LATCH

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MC10E154, MC100E154
5V ECL 5-Bit 2:1 Mux-Latch
Description
The MC10E/100E154 contains five 2:1 multiplexers followed by
transparent latches with differential outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output data is
controlled by the multiplexer select control, SEL. A logic HIGH on
either LEN1 or LEN2 (or both) latches the outputs. The Master Reset
(MR) overrides all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
Features
850 ps Maximum LEN to Output
825 ps Maximum D to Output
Differential Outputs
Asynchronous Master Reset
Dual Latch-Enables
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 237 Devices
PbFree Packages are Available*
http://onsemi.com
PLCC28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE154FNG
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 8
1
Publication Order Number:
MC10E154/D


  ON Semiconductor Electronic Components Datasheet  

MC10E154 Datasheet

5-BIT 2:1 MUX-LATCH

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MC10E154, MC100E154
D4b D4a D3b D3a VCCO Q4 Q4
25 24 23 22 21 20 19
SEL 26
18 Q3
LEN1 27
17 Q3
LEN2 28
16 VCC
VEE 1
MR 2
D0a 3
D0b 4
28-Lead PLCC
(Top View)
15 Q2
14 Q2
13 Q1
12 Q1
5 6 7 8 9 10 11
D1a D1b D2a D2b VCCO Q0 Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28Lead Pinout
Table 1. PIN DESCRIPTION
PIN FUNCTION
D0a D4a
D0b D4b
SEL
ECL Input Data a
ECL Input Data b
ECL Data Select Input
LEN1, LEN2
ECL Latch Enables
MR ECL Master Reset
Q0Q4, Q0 Q4
VCC, VCCO
VEE
ECL Differential Outputs
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
SEL
H
L
DATA
a
b
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
SEL
LEN1
LEN2
MR
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
DQ
ENR Q
DQ
ENR Q
DQ
ENR Q
DQ
ENR Q
DQ
ENR Q
Figure 2. Logic Diagram
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
http://onsemi.com
2


Part Number MC10E154
Description 5-BIT 2:1 MUX-LATCH
Maker ON Semiconductor
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MC10E154 Datasheet PDF






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