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  ON Semiconductor Electronic Components Datasheet  

MC14077B Datasheet

CMOS SSI

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MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
MC14070B — Replacement for CD4030B and CD4070B Types
MC14077B — Replacement for CD4077B Type
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC140XXBCP
AWLYYWW
1
SOIC–14
D SUFFIX
CASE 751A
14
140XXB
AWLYWW
1
SOEIAJ–14
F SUFFIX
CASE 965
14
MC140XXB
AWLYWW
1
XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC140XXBCP
PDIP–14
2000/Box
MC140XXBD
SOIC–14
2750/Box
MC140XXBDR2 SOIC–14 2500/Tape & Reel
MC140XXBF
SOEIAJ–14 See Note 1.
MC140XXBFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14070B/D


  ON Semiconductor Electronic Components Datasheet  

MC14077B Datasheet

CMOS SSI

No Preview Available !

MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MC14070B
MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate
Gate
11
33
22
55
44
66
88
10 10
99
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
VDD
IDD
Vin *
CL
20 ns
Vin
20 ns
90%
50%
10%
1/f
50% DUTY CYCLE
*Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
VSS
VDD 20 ns
PULSE
GENERATOR
#
*
VSS
INPUT
90%
50%
10%
CL tPHL
OUTPUT
90%
50%
10%
*Inverted output on MC14077B only.
tTHL
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
Figure 2. Switching Time Test Circuit and Waveforms
20 ns
VDD
VSS
tPLH
VOH
VOL
tTLH
http://onsemi.com
2


Part Number MC14077B
Description CMOS SSI
Maker ON Semiconductor
Total Page 8 Pages
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